The need for more powerful processing platforms in the avionics industry and the availability of multi-core devices has resulted in the development of avionics processing platforms utilizing multi-core devices. However, before multi-core devices can be utilized in avionics processing platforms, testing should be performed to ensure that the operation of each multi-core device complies with required regulations. For example, it may be a requirement that a display is updated every 50 ms. Before a multi-core device can be utilized, it should be shown to comply with this requirement.
In order to ensure that a multi-core device complies with required regulations, multi-core devices should be able to pass data between cores, processes and threads in a wait-free manner. There should also be no interference between applications running on the multi-core device. That is, each application should be partitioned in memory and time space, such that memory and timing are not affected by the execution of other applications.
Current deterministic solutions for multi-core communication can be divided into blocking and non-blocking algorithms. Blocking algorithms are non-ideal, as threads/cores compete for shared resources and, due to mutual exclusion, can have their execution postponed indefinitely. Current, conventional non-blocking algorithms predominately use atomic read-modify-write primitives that should be provided by the underlying hardware components. Additionally, non-blocking algorithms may require a writer to wait for a reader to complete reading data from a shared resource before the writer is permitted to write data to the shared resource. That is, current non-blocking algorithms may not allow a reader to simultaneously read data from a shared resource as a writer writes data to the shared resource.